1. Field of the Invention
The present invention relates to a hardware-software co-simulation system, a hardware-software co-simulation method, and a computer-readable memory containing a hardware-software co-simulation program, and more particularly to a technology for co-simulating both hardware and software quickly and for verifying software efficiently.
2. Description of the Related Art
FIG. 1 is a block diagram showing a conventional hardware-software co-simulation system. In the conventional hardware-software co-simulation system, register-transfer(RT) level accuracy is required for hardware(HW) oriented verification. Therefore, for a software part, the system uses an RT-level software simulator 13 to perform simulation with input from a small scale software 11, as shown in the figure. This small scale software 11, such as a driver program, of the software to be verified contains only basic instructions with no description of input data from or output data to external units. On the other hand, for a hardware part, the system uses an RT-level hardware simulator 14 to perform simulation with input from an RT-level hardware description 12 describing what the hardware does within one system clock time. Co-simulation of the RT-level software simulator 13 and the RT-level hardware simulator 14 gives a HW verification result 20 for use in verifying the hardware.
The co-simulator with this configuration, primarily designed for verifying the hardware to get RT-level data, takes a huge amount of simulation time because verification for a processor part is also in RT-level. For this reason, a small scale software is used as the input from the software simulator side. Therefore, this configuration is not suitable for software verification.
For software(SW) oriented verification, an instruction-level software simulator 18 executes a verification for a software part by means of the small scale software as well as an application software 16 which includes not only basic Instructions but also external input/output instructions. An instruction-level hardware simulator 19 executes a verification for a hardware part by means of an instruction-level hardware description 23 describing what the hardware does on an instruction basis.
Co-simulation of the instruction-level software simulator 18 and the instruction-level hardware simulator 19 gives an SW verification result 21 for use in verifying the software.
For software oriented verification, hardware simulation at an abstraction degree corresponding to a processor instruction level is enough; this lower-accuracy simulation ensures high-speed simulation. A typical hardware description that is used in this simulation is a behavior-level description.
The problem with this method is that a hardware designer usually creates RT-level description data only, because the current design method is automated on an RT or lower level. This means that creating behavior level description increases the load on the hardware designer. In addition, if behavior-level description data is created successfully, the designer must guarantee that the behavior level description data is equivalent to the corresponding RT level description data. This further increases the load.
To solve this problem, a co-simulator shown in FIG. 2 is disclosed. In this co-simulator, for both software oriented verification and hardware oriented verification, for a software part, the instruction-level software simulator 18 executes instruction-level software simulation by means of the application software program 16 while, for a hardware part, the RT-level hardware simulator 14 executes RT-level hardware simulation by means of the RT-level hardware description 12.
This instruction-level software simulator 18 and the RT-level hardware simulator 14, which differ in the simulation level, cannot work together to perform co-simulation. To convert the level for co-simulation, a level converter 24 is provided. This level converter 24 looks up a data book 25 describing a correspondence between bus cycles of which a processor operates on the basis and signal variations occurred in RT-level to convert an operation in one description into that in another. This conversion allows co-simulation to be performed without creating an instruction-level hardware simulator.
However, the co-simulation system shown in FIG. 2, which has the level converter 24, requires the software part to do instruction-level simulation and, at the same time, the hardware part to do RT-level simulation, simultaneously.
In this system, though the instruction-level software simulator is fast enough for the hardware developer, the RT-level hardware simulator is slow for the software developer, thus degrading the software debugging efficiency.
To perform hardware-software co-simulation quickly, the applicant of the present invention thinks it vital to perform co-simulation for software oriented verification on an instruction level. The applicant also notices that the above problem is caused by the fact that the hardware designer usually creates an RT-level hardware description only, not an instruction-level hardware description.